1. Field of the Invention
The invention relates generally to a method of manufacturing memory devices and, more particularly, to a method of manufacturing a flash memory device, wherein the interference phenomenon between adjacent floating gates can be minimized.
2. Discussion of Related Art
In the manufacturing methods for flash memory devices, the dimensions of spaces in which a unit active region and a unit field region will be formed have decreased in size as such devices have become more highly integrated. As a dielectric layer including a floating gate and a control gate are formed within a narrow active space, the interference phenomenon becomes more problematic since the inter-gate distance is narrowed.
FIGS. 1a and 1b are cross-sectional views illustrating a method of manufacturing a flash memory device to which self-aligned shallow trench isolation (STI) process is applied in the related art.
Referring to FIG. 1a, a tunnel oxide film 11, a first polysilicon layer 12, and a nitride film (not shown) are sequentially formed on a semiconductor substrate 10. The nitride film, the first polysilicon layer 12, the tunnel oxide film 11, and the semiconductor substrate 10 are sequentially etched using an etch process employing an isolation mask, thereby forming trenches.
An insulating film, such as a high density plasma (HDP) oxide film, is formed on the entire structure so that the trenches are buried. The insulating film is polished so that a top surface of the first polysilicon layer 12 is exposed. The nitride film is stripped to form isolation films 13 within the trenches.
A second polysilicon layer 14 is formed on the entire structure. The second polysilicon layer 14 is etched using a mask to form a floating gate including of the first polysilicon layer 12 and the second polysilicon layer 14. A dielectric layer 15 and a conductive layer 16 are sequentially formed on the entire structure and are then patterned using a mask, thereby forming control gates vertical to the isolation films 13.
As semiconductor devices become more highly integrated, however, the width D of the isolation film is reduced and the distance between adjacent first polysilicon layers is reduced accordingly. This generates the interference phenomenon by adjacent first polysilicon layers, which results in the interference phenomenon between the floating gates.
Furthermore, the threshold voltage (Vt) of the semiconductor substrate varies due to the interference phenomenon between the floating gates. This maximizes the interference phenomenon in the direction of the control gate, inevitably resulting in degraded device characteristics.
To solve the problems, if the top surface of the isolation film is etched in order to deepen the etch depth when the floating gate is etched as shown in FIG. 1b, an insulation depth D between the floating gates can be increased to improve the interference phenomenon between the floating gates.
If the etch depth is increased, however, the distance L between the active region and the control gate is narrowed. This results in variation in the cycling threshold voltage (Vt) upon cycling test.